This invention is directed toward a measurement technique used in the manufacture of semiconductor wafers and, more particularly, to determine the registration of overlying semiconductor layers with each other.
The fabrication of complex semiconductor devices on wafers, typically made of silicon, involves multiple processing steps which produce several overlying layers of different materials. The several layers contain corresponding features designed to cooperate with each other. Displacement between corresponding features on different layers can degrade device performance or can cause the devices to be totally inoperative. Consequently, the wafer layers must be precisely registered, or accurately aligned in stacked position relative to each other, to enable proper operation of each device in accordance with its design. As semiconductor devices have become increasingly complex, the dimensions of the features have been correspondingly reduced. This reduction in feature dimensions has reduced acceptable tolerances on displacement between layers. It is standard practice to set the acceptable tolerance at one-third of the process critical line width. For example, in current 0.18 micron technology, the tolerance is 0.06 micron (60 nanometers).
Since such wafers are expensive to fabricate, it is desirable to measure the overlay registration error (sometimes referred to hereinafter as the xe2x80x9cerrorxe2x80x9d) after each lithography process, i.e. after the application, or printing, of each layer onto the wafer, in order to verify that the printed layer is in registration with the previous layer within acceptable tolerances. If the error is outside of the acceptable tolerances, the defective layer can, in some cases, be removed and replaced with an accurately registered layer after the fabrication equipment is suitably adjusted based on the measured error. In other cases, the wafer is scrapped, thereby saving the expense of conducting further processing steps on defective wafers. Also, based on such error measurements, it is possible to collect statistical process control (xe2x80x9cSPCxe2x80x9d) data to track the overlay registration errors over time for use in controlling the wafer fabrication process.
A lithography tool is a machine which is essential to wafer fabrication. It places the designed image on the wafer. One such lithography tool is a stepper. For ease of explanation, the word stepper is used herein to represent all types of lithography tools. A stepper places the designed image on the wafer in an array of stepper fields. Each stepper field can include, for example, an array of dies that will be made into electronic components when the wafer is cut along scribe lines. To assist in overlay verification measurements, also known as in-process metrology, it has been common practice to provide each stepper field with a number of registration marks, or targets. For example, a target can be placed in each corner of the stepper field and perhaps another one in its interior area. One version of such a target, known as the xe2x80x9cbox in boxxe2x80x9d, is shown in FIGS. 1 and 2. Target 1 on wafer 3 includes patterns 5 and 9 formed on layers 7 and 11, respectively. For example, xe2x80x9cinnerxe2x80x9d pattern 5 is usually a solid square of photoresist, and xe2x80x9couterxe2x80x9d pattern 9 is usually formed on a substrate layer. Typically, pattern 5 is a 10 micron square and pattern 9 is a 20 micron square.
Other versions of the target are known as xe2x80x9cframe in framexe2x80x9d (see 15 in FIG. 3) and xe2x80x9cbar in barxe2x80x9d (see 17 in FIG. 4). These are substantially the same in that the corners of target 15 are left out to form target 17. More specifically, outer pattern 19 of target 15 is a set of segments 21-24 joined together to form a continuous wall 15A. Outer pattern 19xe2x80x2 of target 17 is a set of segments 21xe2x80x2-24xe2x80x2 which are not joined to each other. A cross section of both targets is shown in FIG. 5. Pattern 5 in FIGS. 3 and 4 can be the same solid pattern as shown in FIGS. 1 and 2. Alternatively, it can be a frame or a bar pattern also.
The word xe2x80x9cpatternxe2x80x9d as used herein broadly refers to any geometric shape that is recognizable by an automated metrology system for the purpose of making overlay registration measurements. The shape can be the external periphery of one body, such as solid square 5, or it can be defined by a plurality of bodies, connected to each other or not, such as the segments 21-24 and 21xe2x80x2-24xe2x80x2.
Automated metrology systems for performing a two-layer overlay registration error measurement are well known. Such a system generates an optical image of the target which is recorded by a CCD camera, and the image is digitized. The digitized image is processed to determine the center position of a pattern. A standard technique for center measurement used in two-layer overlay registration error measurements is to locate the edges of the pattern. There are a number of well known algorithms available to do this, such as pure centroid (center of gravity) and best fit calculations. Once the edges have been located, and since the patterns of the two-layer targets are defined as having a square shape, the center is the direct average of the two horizontal (for y value) and vertical (for x value) edge locations. Such a technique, known as xe2x80x9cSmart Plusxe2x80x9d, is used in the model IVS 120 system available from Schlumberger Verification Systems in Concord, Mass. The portion of the IVS 120 User""s Manual relevant to this technique is hereby incorporated by reference.
The overlay registration error between two layers is determined by calculating the difference between the center of the outer pattern and the center of the inner pattern. Once the centers of both patterns are known, the overlay registration error is determined by subtracting the inner pattern center from the outer pattern center. This can be expressed by the following relationship:
Overlay Registration Error=(Orxe2x88x92Ol)xe2x88x92(Irxe2x88x92Il), (Obxe2x88x92Ot)xe2x88x92(Ibxe2x88x92It)
where
Or is the x value for the outer pattern right edge;
Ol is the x value for the outer pattern left edge;
Ob is the y value for the outer pattern bottom edge;
Ot is the y value for the outer pattern top edge;
Ir is the x value for the inner pattern right edge;
Il is the x value for the inner pattern left edge;
Ib is the y value for the inner pattern bottom edge;
It is the y value for the inner pattern top edge.
This derived error is expressed as x,y values that can be mapped onto a statistical plot which displays the limits of the acceptable tolerances. By plotting the x,y values of the derived error, the stepper operator can readily determine whether or not the process is within spec (i.e. the acceptable tolerances have not been exceeded). Moreover, the plotted results may even assist in guiding the operator to make the necessary adjustment in re-applying the defective layer to avoid a repetition of the misregistration. Various types of such plots, as well as diagrams, charts and tables used for process control purposes, are well known and in conventional usage, and selecting a particular one is a matter of design choice.
Automated techniques are also available to provide pass/fail/adjust data based on the two-layer overlay registration measurement error. The error value is used as an input which results in a stepper correction being generated automatically. One such technique is described in a paper by Edward A. Mc Fadden and Christopher P. Ausschnitt titled xe2x80x9cA Computer Aided Engineering Workstation for Registration Controlxe2x80x9d, published in SPIE Vol. 1087 of Integrated Circuit Metrology, Inspection, and Process Control III (1989), pages 255-266. This paper is hereby incorporated by reference.
It is not sufficient to measure only the overlay between two layers to insure that they are within the acceptable tolerances because for some layer combinations the overlay is critical among more than just two layers (referred to broadly hereinafter as xe2x80x9cmulti-layerxe2x80x9d overlay). As is well known, one such layer combination includes an active substrate layer (e.g. nitride), a polysilicon layer and a first contact (i.e. metalization) layer. This is probably the most critical tolerance in a wafer fabrication process. The first contact layer must be precisely aligned to both the polysilicon and nitride layers within tight tolerances. Even if the permissible 60 nanometer error (for 0.18 micron technology) occurs between each of the polysilicon/nitride two-layer overlay and the first contact/polysilicon two-layer overlay, the possible maximum resulting total overlay registration error of 120 nanometers for the first contact/nitride overlay would be well beyond its acceptable tolerances which is also 60 nanometers.
Tri-layer measurements have been made for years by the semiconductor wafer manufacturers (wafer fabs). However, none has put these measurements together in a single process that will save time, increase throughput, and automate the stepper adjustment process. The method that wafer fabs most commonly use currently is to do two separate two-layer overlay measurements (e.g. nitride/first contact and polysilicon/first contact) to provide a pass-fail criterion for the wafer. However, this has several disadvantages. Firstly, it takes twice as long to do two separate two-layer measurements as it does to do one two-layer measurement. Consequently, this approach reduces throughput. Secondly, stepper adjustments cannot simply be made for one layer to correct a multi-layer overlay registration error because the adjustment for one two-layer overlay is not independent of adverse effects on the other two-layer overlay. Consequently, a multi-layer overlay registration error derived this way often requires the intervention of a process engineer to determine the needed adjustment to the stepper. The engineer must then guess as to the correct adjustment since the data for one of the two-layer overlays is presented separately from the other. This reliance on skilled labor is costly, and the entire operation further adds to the time required to adjust the stepper, with attendant adverse consequences on throughput.
One object of the present invention is to provide an improved technique for measuring registration of overlying semiconductor layers with each other.
Another object of the present invention is to enable simultaneously measuring registration of more than two overlying semiconductor layers with each other.
Yet another object of the present invention is to provide a target for multi-layer overlay registration verification which requires no more wafer surface space then a two-layer overlay target.
A further object of the present invention is to develop a target that will allow measuring registration among more than two overlying semiconductor layers at once.
One other object of the present invention is to develop a methodology that will allow measuring registration among more than two overlying semiconductor layers at once and obtain a useful overlay registration error measurement.
Yet another object of the present invention is to facilitate wafer processing in case of an overlay registration error among more than two overlying semiconductor layers without the intervention of a process engineer.
Another object of the present invention is to provide improved throughput when conducting and analyzing a multi-layer overlay registration error measurement.
These and other objects are attained in accordance with one aspect of the present invention directed to a method for forming a target used to measure registration relative to each other of more than two layers of a semiconductor wafer. At least first, second and third layers are formed to overlay each other. A first pattern is provided in a designated location of the first layer. A second pattern is provided in a designated location of the second layer, such second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location. A third pattern is provided in a designated location of the third layer, such third pattern having the given shape and the given size of the second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of the second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other.
Another aspect of the present invention is directed to a method for measuring registration relative to each other of more than two layers of a semiconductor wafer. At least first, second and third layers are formed to overlay each other. A first pattern is provided in a designated location of the first layer. A second pattern is provided in a designated location of the second layer, such second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location. A third pattern is provided in a designated location of the third layer, such third pattern having the given shape and the given size of the second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of the second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other. The method further includes measuring an overlay registration error between the first pattern and each of the second and third patterns.
Another aspect of the present invention is directed to a method for measuring registration relative to each other of more than two layers of a semiconductor wafer being fabricated with a stepper controlled to position a plurality of stepper fields to apply each layer of the wafer. A first pattern is provided in a designated location of a stepper field forming a first layer. A second pattern is provided in a designated location of a stepper field forming a second layer, such second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location. A third pattern is provided in a designated location of a stepper field forming a third layer, such third pattern having the given shape and the given size of the second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of the second and third patterns fits within at least one discontinuity in the other when the second and third layers are in registration with each other. The method further includes measuring an overlay registration error between the first pattern and each of the second and third patterns.
Another aspect of the present invention is directed to a method for fabricating a semiconductor wafer. At least first, second and third layers are formed to overlay each other. A first pattern is provided in a designated location of the first layer. A second pattern is provided in a designated location of the second layer, such second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location. A third pattern is provided in a designated location of the third layer, such third pattern having the given shape and the given size of the second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of the second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other. A first overlay registration error is measured between the first pattern and the second pattern. A second overlay registration error is measured between the first pattern and the third pattern. An average error of said first and second overlay registration measurement errors is obtained, and further processing of the wafer is automatically determined based on the average error.
Another aspect of the present invention is directed to an apparatus to automatically control a process for fabricating a semiconductor wafer. The apparatus includes means for forming at least first, second and third layers which overlay each other, and means for providing a first pattern in a designated location of the first layer. The apparatus also includes means for providing a second pattern in a designated location of the second layer, such second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location. Another means is included for providing a third pattern in a designated location of the third layer, such third pattern having the given shape and the given size of the second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of the second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other. A measuring means measures a first overlay registration error between the first pattern and the second pattern, and another measuring means measures a second overlay registration error between the first pattern and the third pattern. The apparatus also includes means for obtaining an average error of the first and second overlay registration measurement errors, and control means for automatically determining further processing of the wafer based on the average error.